wiebel
6 years ago
6 changed files with 7433 additions and 0 deletions
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(module OWN_DC-DC (layer F.Cu) (tedit 0) |
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(fp_text reference Ref** (at 0 0) (layer F.SilkS) |
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(effects (font (size 1.27 1.27) (thickness 0.15))) |
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) |
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(fp_text value Val** (at 0 0) (layer F.SilkS) |
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(effects (font (size 1.27 1.27) (thickness 0.15))) |
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) |
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(fp_line (start -17.145 -10.795) (end -17.145 0.635) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -17.145 0.635) (end 0.635 0.635) (layer F.SilkS) (width 0.127)) |
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(fp_line (start 0.635 0.635) (end 0.635 -10.795) (layer F.SilkS) (width 0.127)) |
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(fp_line (start 0.635 -10.795) (end -17.145 -10.795) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -17.145 -10.795) (end -17.145 0.635) (layer B.SilkS) (width 0.127)) |
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(fp_line (start -17.145 -10.795) (end 0.635 -10.795) (layer B.SilkS) (width 0.127)) |
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(fp_line (start 0.635 0.635) (end 0.635 -10.795) (layer B.SilkS) (width 0.127)) |
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(fp_line (start 0.635 0.635) (end -17.145 0.635) (layer B.SilkS) (width 0.127)) |
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(fp_text user +IN (at -15.24 -8.89) (layer F.SilkS) |
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(effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) |
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) |
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(fp_text user OUT+ (at -1.27 -8.89) (layer F.SilkS) |
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(effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right bottom)) |
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) |
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(fp_text user GND (at -8.255 0) (layer F.SilkS) |
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(effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify bottom)) |
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) |
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(fp_text user +IN (at -15.24 -8.89) (layer B.SilkS) |
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(effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right bottom mirror)) |
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) |
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(fp_text user OUT+ (at -1.27 -8.89) (layer B.SilkS) |
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(effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom mirror)) |
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) |
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(fp_text user GND (at -8.255 0) (layer B.SilkS) |
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(effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify bottom mirror)) |
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) |
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(pad IN+ thru_hole rect (at -15.875 -9.525) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad IN- thru_hole rect (at -15.875 -0.635) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad OUT+ thru_hole rect (at -0.635 -9.525) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad OUT- thru_hole rect (at -0.635 -0.635) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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) |
@ -0,0 +1,40 @@ |
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(module OWN_KF141V-P4_simple (layer F.Cu) (tedit 5BE8AF3A) |
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(fp_text reference >NAME (at -10.16 1.27 90) (layer F.SilkS) |
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(effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left)) |
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) |
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(fp_text value Val** (at 0 0) (layer F.SilkS) |
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(effects (font (size 1.27 1.27) (thickness 0.15))) |
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) |
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(fp_line (start -11.59 -8.08) (end -11.59 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -11.59 -8.08) (end -9.09 -8.08) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -9.09 -8.08) (end -6.55 -8.08) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -6.55 -8.08) (end -4.01 -8.08) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -4.01 -8.08) (end -1.47 -8.08) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -1.47 2.42) (end -4.01 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -4.01 2.42) (end -6.55 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -6.55 2.42) (end -9.09 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -9.09 2.42) (end -11.59 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -9.09 -8.08) (end -9.09 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -6.55 -8.08) (end -6.55 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -4.01 -8.08) (end -4.01 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -1.47 -8.08) (end -1.47 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start 1.07 -8.08) (end 1.07 2.42) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -1.43 -8.08) (end 1.07 -8.08) (layer F.SilkS) (width 0.127)) |
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(fp_line (start -1.43 2.42) (end 1.07 2.42) (layer F.SilkS) (width 0.127)) |
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(pad 1 thru_hole oval (at -7.62 0 90) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad 2 thru_hole oval (at -5.08 0 90) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad 3 thru_hole oval (at -2.54 0 90) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad 4 thru_hole oval (at 0 0 90) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad 1 thru_hole oval (at -7.62 -5.08 90) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad 2 thru_hole oval (at -5.08 -5.08 90) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad 3 thru_hole oval (at -2.54 -5.08 90) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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(pad 4 thru_hole oval (at 0 -5.08 90) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask) |
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(solder_mask_margin 0.1016)) |
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) |
@ -0,0 +1,43 @@ |
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update=Sa 10 Nov 2018 01:38:57 CET |
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version=1 |
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last_client=kicad |
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[general] |
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version=1 |
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RootSch= |
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BoardNm= |
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[pcbnew] |
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version=1 |
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LastNetListRead= |
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UseCmpFile=1 |
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PadDrill=0.600000000000 |
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PadDrillOvalY=0.600000000000 |
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PadSizeH=1.500000000000 |
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PadSizeV=1.500000000000 |
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PcbTextSizeV=1.500000000000 |
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PcbTextSizeH=1.500000000000 |
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PcbTextThickness=0.300000000000 |
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ModuleTextSizeV=1.000000000000 |
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ModuleTextSizeH=1.000000000000 |
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ModuleTextSizeThickness=0.150000000000 |
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SolderMaskClearance=0.000000000000 |
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SolderMaskMinWidth=0.000000000000 |
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DrawSegmentWidth=0.200000000000 |
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BoardOutlineThickness=0.100000000000 |
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ModuleOutlineThickness=0.150000000000 |
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[cvpcb] |
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version=1 |
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NetIExt=net |
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[eeschema] |
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version=1 |
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LibDir= |
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[eeschema/libraries] |
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[schematic_editor] |
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version=1 |
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PageLayoutDescrFile= |
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PlotDirectoryName= |
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SubpartIdSeparator=0 |
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SubpartFirstId=65 |
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NetFmtName= |
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SpiceAjustPassiveValues=0 |
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LabSize=50 |
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ERC_TestSimilarLabels=1 |
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