pproaching v2.5
This commit is contained in:
parent
d32e0b6ee5
commit
e1f4675ef8
@ -1,18 +1,46 @@
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# CANNode-rescue_DSN-MINI-360-000_my_lib
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# 00_mylib_Logo
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#
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DEF CANNode-rescue_DSN-MINI-360-000_my_lib MOD 0 40 N Y 1 F N
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F0 "MOD" 350 -50 50 H V C CNN
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F1 "CANNode-rescue_DSN-MINI-360-000_my_lib" 200 350 50 H V C CNN
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F2 "" 250 150 50 H I C CNN
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F3 "" 250 150 50 H I C CNN
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DEF 00_mylib_Logo Log 0 0 N N 1 F N
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F0 "Log" 0 0 50 H I C CNN
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F1 "00_mylib_Logo" 0 100 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S 0 300 400 0 0 0 0 f
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X GND GND 200 -100 100 U 50 50 1 1 P
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X IN IN -100 250 100 R 50 50 1 1 P
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X OUT OUT 500 250 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# 00_mylib_OWN_DCDC-CANNode
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#
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DEF 00_mylib_OWN_DCDC-CANNode MOD 0 40 N N 1 L N
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F0 "MOD" 0 0 45 H I C CNN
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F1 "00_mylib_OWN_DCDC-CANNode" 0 0 45 H I C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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*OWN_DC-DC*
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$ENDFPLIST
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DRAW
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T 0 -174 128 56 0 1 0 + Normal 0 C C
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T 0 226 128 56 0 1 0 + Normal 0 C C
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T 0 7 28 56 0 1 0 DCDC Normal 0 C C
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S -150 100 150 -50 1 1 0 N
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P 2 1 0 0 -300 -200 300 -200 N
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P 2 1 0 0 -300 -100 -300 -200 N
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P 2 1 0 0 -300 -100 0 -100 N
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P 2 1 0 0 -300 200 -300 -100 N
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P 2 1 0 0 -30 -150 30 -150 N
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P 2 1 0 0 0 -100 0 -150 N
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P 2 1 0 0 0 -100 300 -100 N
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P 2 1 0 0 300 -200 300 -100 N
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P 2 1 0 0 300 -100 300 200 N
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P 2 1 0 0 300 200 -300 200 N
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X IN+ IN+ -400 100 200 R 40 40 1 1 W
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X IN- IN- -400 -100 200 R 40 40 1 1 W
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X OUT+ OUT+ 400 100 200 L 40 40 1 1 w
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X OUT- OUT- 400 -100 200 L 40 40 1 1 w
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ENDDRAW
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ENDDEF
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#
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@ -61,6 +89,27 @@ X 7_RX3_DOUT 9 -950 -100 200 R 50 50 1 1 B
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ENDDRAW
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ENDDEF
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#
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# Connector_Generic_Conn_01x03
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#
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DEF Connector_Generic_Conn_01x03 J 0 40 Y N 1 F N
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F0 "J" 0 200 50 H V C CNN
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F1 "Connector_Generic_Conn_01x03" 0 -200 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_1x??_*
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$ENDFPLIST
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DRAW
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 105 0 95 1 1 6 N
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S -50 150 50 -150 1 1 10 f
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X Pin_1 1 -200 100 150 R 50 50 1 1 P
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X Pin_2 2 -200 0 150 R 50 50 1 1 P
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X Pin_3 3 -200 -100 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Connector_Generic_Conn_01x04
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#
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DEF Connector_Generic_Conn_01x04 J 0 40 Y N 1 F N
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@ -204,6 +253,9 @@ F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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SolderJumper*Bridged*
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Jumper*
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TestPoint*2Pads*
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TestPoint*Bridge*
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$ENDFPLIST
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DRAW
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A 0 -10 57 450 1350 0 1 0 N 40 30 -40 30
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@ -328,7 +380,9 @@ F1 "Jumper_Jumper_3_Bridged12" 0 110 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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SolderJumper*Bridged12*
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Jumper*
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TestPoint*3Pads*
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TestPoint*Bridge*
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$ENDFPLIST
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DRAW
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A -65 -50 89 1282 518 0 1 0 N -120 20 -10 20
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@ -342,6 +396,21 @@ X B 3 250 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Mechanical_MountingHole
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#
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DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
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F0 "H" 0 200 50 H V C CNN
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F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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MountingHole*
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$ENDFPLIST
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DRAW
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C 0 0 50 0 1 50 N
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ENDDRAW
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ENDDEF
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#
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# power_+12V
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#
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DEF power_+12V #PWR 0 0 Y Y 1 F P
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File diff suppressed because it is too large
Load Diff
@ -1,29 +1,10 @@
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update=Sat Nov 16 21:58:46 2019
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update=Tue 30 Jun 2020 09:41:16 PM CEST
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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@ -41,3 +22,246 @@ NetFmtName=Pcbnew
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=CANNode.net
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CopperLayerCount=4
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.1524
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MinViaDiameter=0.6858
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MinViaDrill=0.3302
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth1=0.3
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TrackWidth2=0.175
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TrackWidth3=0.2
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TrackWidth4=0.25
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TrackWidth5=0.3
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TrackWidth6=0.4
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TrackWidth7=0.6
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TrackWidth8=0.8
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TrackWidth9=1.6
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ViaDiameter1=0.6858
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ViaDrill1=0.3302
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dPairWidth1=0.3
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dPairGap1=0.175
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dPairViaGap1=0.25
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SilkLineWidth=0.15
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SilkTextSizeV=1
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SilkTextSizeH=1
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SilkTextSizeThickness=0.15
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.2
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.2
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CourtyardLineWidth=0.05
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OthersLineWidth=0.15
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0.2
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SolderMaskMinWidth=0.25
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Layer.F.Cu]
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Name=F.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.In1.Cu]
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Name=In1.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.In2.Cu]
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Name=In2.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.In3.Cu]
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Name=In3.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In4.Cu]
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Name=In4.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In5.Cu]
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Name=In5.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In6.Cu]
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Name=In6.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In7.Cu]
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Name=In7.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In8.Cu]
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Name=In8.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In9.Cu]
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Name=In9.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In10.Cu]
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Name=In10.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In11.Cu]
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Name=In11.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In12.Cu]
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Name=In12.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In13.Cu]
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Name=In13.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In14.Cu]
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Name=In14.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In15.Cu]
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Name=In15.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In16.Cu]
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Name=In16.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In17.Cu]
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Name=In17.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In18.Cu]
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Name=In18.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In19.Cu]
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Name=In19.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In20.Cu]
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Name=In20.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In21.Cu]
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Name=In21.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In22.Cu]
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Name=In22.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In23.Cu]
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Name=In23.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In24.Cu]
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Name=In24.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In25.Cu]
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Name=In25.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In26.Cu]
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Name=In26.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In27.Cu]
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Name=In27.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In28.Cu]
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Name=In28.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In29.Cu]
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Name=In29.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In30.Cu]
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Name=In30.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.B.Cu]
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Name=B.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.B.Adhes]
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Enabled=1
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[pcbnew/Layer.F.Adhes]
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Enabled=1
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[pcbnew/Layer.B.Paste]
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Enabled=1
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[pcbnew/Layer.F.Paste]
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Enabled=1
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[pcbnew/Layer.B.SilkS]
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Enabled=1
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[pcbnew/Layer.F.SilkS]
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Enabled=1
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[pcbnew/Layer.B.Mask]
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Enabled=1
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[pcbnew/Layer.F.Mask]
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Enabled=1
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[pcbnew/Layer.Dwgs.User]
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Enabled=1
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[pcbnew/Layer.Cmts.User]
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Enabled=1
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[pcbnew/Layer.Eco1.User]
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Enabled=1
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[pcbnew/Layer.Eco2.User]
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Enabled=1
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[pcbnew/Layer.Edge.Cuts]
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Enabled=1
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[pcbnew/Layer.Margin]
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Enabled=1
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[pcbnew/Layer.B.CrtYd]
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Enabled=1
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[pcbnew/Layer.F.CrtYd]
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Enabled=1
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[pcbnew/Layer.B.Fab]
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Enabled=1
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[pcbnew/Layer.F.Fab]
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Enabled=1
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[pcbnew/Layer.Rescue]
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Enabled=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/Default]
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Name=Default
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Clearance=0.175
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TrackWidth=0.3
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ViaDiameter=0.6858
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ViaDrill=0.3302
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uViaDiameter=0.3
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uViaDrill=0.1
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dPairWidth=0.3
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dPairGap=0.175
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dPairViaGap=0.25
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[pcbnew/Netclasses/1]
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Name=Power
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Clearance=0.2
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TrackWidth=0.5
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ViaDiameter=1.25
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ViaDrill=0.5
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uViaDiameter=0.65
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uViaDrill=0.2
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dPairWidth=0.3
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dPairGap=0.25
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dPairViaGap=0.25
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File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user