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pproaching v2.5

master
wiebel 4 years ago
parent
d32e0b6ee5
commit
e1f4675ef8
4 changed files with 10278 additions and 13178 deletions
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  1. 91
      Hardware/kicad/CANNode-cache.lib
  2. 21918
      Hardware/kicad/CANNode.kicad_pcb
  3. 264
      Hardware/kicad/CANNode.pro
  4. 1183
      Hardware/kicad/CANNode.sch

91
Hardware/kicad/CANNode-cache.lib
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@ -1,18 +1,46 @@
EESchema-LIBRARY Version 2.4 EESchema-LIBRARY Version 2.4
#encoding utf-8 #encoding utf-8
# #
# CANNode-rescue_DSN-MINI-360-000_my_lib # 00_mylib_Logo
# #
DEF CANNode-rescue_DSN-MINI-360-000_my_lib MOD 0 40 N Y 1 F N DEF 00_mylib_Logo Log 0 0 N N 1 F N
F0 "MOD" 350 -50 50 H V C CNN F0 "Log" 0 0 50 H I C CNN
F1 "CANNode-rescue_DSN-MINI-360-000_my_lib" 200 350 50 H V C CNN F1 "00_mylib_Logo" 0 100 50 H V C CNN
F2 "" 250 150 50 H I C CNN F2 "" 0 0 50 H I C CNN
F3 "" 250 150 50 H I C CNN F3 "" 0 0 50 H I C CNN
DRAW DRAW
S 0 300 400 0 0 0 0 f ENDDRAW
X GND GND 200 -100 100 U 50 50 1 1 P ENDDEF
X IN IN -100 250 100 R 50 50 1 1 P #
X OUT OUT 500 250 100 L 50 50 1 1 P # 00_mylib_OWN_DCDC-CANNode
#
DEF 00_mylib_OWN_DCDC-CANNode MOD 0 40 N N 1 L N
F0 "MOD" 0 0 45 H I C CNN
F1 "00_mylib_OWN_DCDC-CANNode" 0 0 45 H I C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
*OWN_DC-DC*
$ENDFPLIST
DRAW
T 0 -174 128 56 0 1 0 + Normal 0 C C
T 0 226 128 56 0 1 0 + Normal 0 C C
T 0 7 28 56 0 1 0 DCDC Normal 0 C C
S -150 100 150 -50 1 1 0 N
P 2 1 0 0 -300 -200 300 -200 N
P 2 1 0 0 -300 -100 -300 -200 N
P 2 1 0 0 -300 -100 0 -100 N
P 2 1 0 0 -300 200 -300 -100 N
P 2 1 0 0 -30 -150 30 -150 N
P 2 1 0 0 0 -100 0 -150 N
P 2 1 0 0 0 -100 300 -100 N
P 2 1 0 0 300 -200 300 -100 N
P 2 1 0 0 300 -100 300 200 N
P 2 1 0 0 300 200 -300 200 N
X IN+ IN+ -400 100 200 R 40 40 1 1 W
X IN- IN- -400 -100 200 R 40 40 1 1 W
X OUT+ OUT+ 400 100 200 L 40 40 1 1 w
X OUT- OUT- 400 -100 200 L 40 40 1 1 w
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
@ -61,6 +89,27 @@ X 7_RX3_DOUT 9 -950 -100 200 R 50 50 1 1 B
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# Connector_Generic_Conn_01x03
#
DEF Connector_Generic_Conn_01x03 J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Connector_Generic_Conn_01x03" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 150 50 -150 1 1 10 f
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x04 # Connector_Generic_Conn_01x04
# #
DEF Connector_Generic_Conn_01x04 J 0 40 Y N 1 F N DEF Connector_Generic_Conn_01x04 J 0 40 Y N 1 F N
@ -204,6 +253,9 @@ F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN F3 "" 0 0 50 H I C CNN
$FPLIST $FPLIST
SolderJumper*Bridged* SolderJumper*Bridged*
Jumper*
TestPoint*2Pads*
TestPoint*Bridge*
$ENDFPLIST $ENDFPLIST
DRAW DRAW
A 0 -10 57 450 1350 0 1 0 N 40 30 -40 30 A 0 -10 57 450 1350 0 1 0 N 40 30 -40 30
@ -328,7 +380,9 @@ F1 "Jumper_Jumper_3_Bridged12" 0 110 50 H V C CNN
F2 "" 0 0 50 H I C CNN F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN F3 "" 0 0 50 H I C CNN
$FPLIST $FPLIST
SolderJumper*Bridged12* Jumper*
TestPoint*3Pads*
TestPoint*Bridge*
$ENDFPLIST $ENDFPLIST
DRAW DRAW
A -65 -50 89 1282 518 0 1 0 N -120 20 -10 20 A -65 -50 89 1282 518 0 1 0 N -120 20 -10 20
@ -342,6 +396,21 @@ X B 3 250 0 100 L 50 50 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# Mechanical_MountingHole
#
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
F0 "H" 0 200 50 H V C CNN
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*
$ENDFPLIST
DRAW
C 0 0 50 0 1 50 N
ENDDRAW
ENDDEF
#
# power_+12V # power_+12V
# #
DEF power_+12V #PWR 0 0 Y Y 1 F P DEF power_+12V #PWR 0 0 Y Y 1 F P

21918
Hardware/kicad/CANNode.kicad_pcb
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File diff suppressed because it is too large

264
Hardware/kicad/CANNode.pro
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@ -1,29 +1,10 @@
update=Sat Nov 16 21:58:46 2019 update=Tue 30 Jun 2020 09:41:16 PM CEST
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
version=1 version=1
RootSch= RootSch=
BoardNm= BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb] [cvpcb]
version=1 version=1
NetIExt=net NetIExt=net
@ -41,3 +22,246 @@ NetFmtName=Pcbnew
SpiceAjustPassiveValues=0 SpiceAjustPassiveValues=0
LabSize=50 LabSize=50
ERC_TestSimilarLabels=1 ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=CANNode.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.6858
MinViaDrill=0.3302
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.3
TrackWidth2=0.175
TrackWidth3=0.2
TrackWidth4=0.25
TrackWidth5=0.3
TrackWidth6=0.4
TrackWidth7=0.6
TrackWidth8=0.8
TrackWidth9=1.6
ViaDiameter1=0.6858
ViaDrill1=0.3302
dPairWidth1=0.3
dPairGap1=0.175
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.2
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.175
TrackWidth=0.3
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.3
dPairGap=0.175
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Power
Clearance=0.2
TrackWidth=0.5
ViaDiameter=1.25
ViaDrill=0.5
uViaDiameter=0.65
uViaDrill=0.2
dPairWidth=0.3
dPairGap=0.25
dPairViaGap=0.25

1183
Hardware/kicad/CANNode.sch
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